Single event upset is an important parameter of radiation reinforcement. One-time single event upset or soft error refers to a non-destructive data transformation on a data storage bit. Charged particles (such as cosmic rays or trapped protons) are incident into a semiconductor device and quickly lose their energies because of interaction with semiconductor materials. The energies lost enable the electrons to jump from a valence band to a conduction band, thus the conduction band has electrons and the valence band has holes, forming electrons-hole pairs, which leads to unbalanced carriers. When there is no electric field, the unbalanced carriers will diffuse, recombine and finally disappear. When there is an electric field, the unbalanced carriers (electron-hole pairs) will separate and be collected by electrodes to form transient current. The transient current will change the node potential and cause a turnover of the logical state of the device; or the transient current will propagate along a signal transmission path, thus interfering the normal function of the circuit. For a memory cell of CMOS SRAM, the reverse-biased PN junction space charge region in the drain region of an off-state transistor become the single event upset sensitive region of the device, whose electric field is strong enough to make the electron-cavity pairs separated and collected by electrodes.
Currently, a typical memory cell has a 6T structure. As shown in FIG. 1, a 6T SRAM unit includes two identical inverters in cross connection, which form a latch circuit, namely, an output of one inverter is connected to an input of another inverter. The latch circuit is connected between a power supply and a ground potential. Each inverter comprises an NMOS pull-down transistor N1 or N2 and a PMOS pull-up transistor P1 or P2. Outputs of the inverter are two storage nodes Q and QB. When one of the storage nodes is pulled down to a low voltage, the other storage node will be pulled up to a high voltage, thus forming a complementary pair. A pair of complementary bit lines BL and BLB are connected to the storage nodes Q and QB via a pair of transmission gate transistors N3 and N4. Gates of the transmission gate transistors N3 and N4 are connected to a word line WL.
Suppose that the state of the memory cell is “1”, namely, Q is a high level and QB is a low level, P1 and N2 transistors are turned on and N1 and P2 transistors are turned off, and a reverse-biased PN junction space charge region in the drain regions of N1 and P2 transistors is the single event upset sensitive region of the device. With respect to N1 transistor, the transient current causes the voltage of the drain (i.e. Q storage point) to drop and be coupled to gates of P2 and N2, thus turning off N2 transistor and turning on P2 transistor, voltage of the drain (i.e. QB storage point) of N2 transistor is raised and fed back to gates of P1 and N1 transistors, thus turning off P1 transistor and turning on N1 transistor, and the state of the memory cell changes thoroughly from “1” into “0”. That is, in a radiation environment, single event upset is liable to occur in the memory cell with a 6T structure, which influences the contents stored, and the wrong value will remain until the memory cell is rewritten next time.
In order to solve the problem of single event upset in the memory cell caused by high-energy particles (high-energy protons, heavy ions) hitting the storage node, usually the two measures of process reinforcement and circuit design reinforcement are adopted. There are usually three methods for circuit design reinforcement. The first method is to add a capacitance or resistance delay element in a storage node of the memory cell, as shown in FIG. 2 and FIG. 3. When the incidence of charged particles causes a potential of the drain of N1 transistor to drop to a low voltage while P1 transistor is still on, the memory cell is in an unstable state, and there is a contention between two processes. On the one hand, a power supply charges a gate capacitor of N2 transistor through P1 to cause the drain voltage of N1 transistor to rise and thus restore to the initial state; on the other hand, the drain voltage of N1 transistor drops to couple to another inverter gate, and is then fed back to turn on N1 transistor and turn off P1 transistor, thus the state of the memory cell is reversed. By increasing RC delay, the transient current delays the time of overturning the logical circuit, thus allowing the node voltage change caused by the peak transient current to have time to restore to the initial value. Disadvantages of said method include a large resistance-capacitance value is needed on the chip, the area of the resistance-capacitance is too large, and the time of write increases greatly. The second method is to add coupling capacitors between two storage nodes, as shown in FIG. 4. The principle of said method is that when one of the nodes is hit by high-energy particles, the transient current generated makes the voltage of one of the nodes to jump, and the voltage of the other node jumps in the same direction under the influence of the coupling capacitors, so that the memory cell cannot be reversed. This method is also limited by the difficulty and area of manufacturing the capacitor and by the time of write. The third method is to use a multi-transistor element to realize redundant preservation of the stored information, as shown by the 12T DICE structure in FIG. 5. Four inverters are connected end to end, wherein the storage nodes are respectively connected to NMOS of the previous stage and to PMOS of the subsequent stage, so that both forward and backward storage data are redundantly preserved, and once a certain storage node has single event upset, the connected node voltage will only influence storage nodes of the previous or subsequent stage, and the stage that is not influenced restores information on the jumped storage node. The disadvantages of said method include requiring too many transistors and occupying too large an area.